1. Technical Field
This invention generally relates to systems modeling and development, and more specifically relates to hardware simulators and emulators.
2. Background Art
The proliferation of modem electronics into our everyday life is due in large part to the existence, functionality and relatively low cost of advanced integrated circuits. As technology moves ahead, the sophistication of integrated circuits increases. Today, our society is heavily dependant upon integrated circuits for everyday activity.
As technology continues to progress, new processing methods and circuit designs continue to drive the performance of integrated circuits and electronic systems higher. Integrated circuits and systems that existed only as designs a few short years ago have already entered production, been marketed, and are becoming obsolete today. In order to be competitive in this rapidly evolving environment, it is necessary for technology-based companies to quickly and efficiently design and test new integrated circuits and systems that take advantage of the latest technological advances.
When designing a new integrated circuit or electronic system, it is often necessary to determine how the new circuit or system will interact with and respond to other circuits or systems. Without a thorough understanding of the performance characteristics and operational parameters associated with a new integrated circuit or system, significant problems may surface once manufacturing and distribution begin. While a proposed integrated circuit or system could actually be manufactured in limited numbers for testing and evaluation purposes, it is usually more convenient, less time-consuming, less costly, and more efficient to create a model or functional prototype of the proposed system. This modeling is typically accomplished by using one or more of the following: 1) simulation systems that model hardware function and performance in software; 2) hardware-assisted software simulation systems; 3) hardware emulation systems that use a combination of software and hardware to model a circuit or system design. All three of these modeling techniques typically operate on a xe2x80x9cnetlistxe2x80x9d, which is a typical output format for many hardware description languages, such as Verilog and Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL).
Simulation or emulation of an integrated circuit or electronic system becomes much more complicated when multiple independent clocks are present in the design. A system with multiple independent clocks is said to have multiple clock domains. A design that has multiple clock domains is difficult to model with a synchronous system. Known techniques for cycle simulation attempt to model multiple clock domains by using a base cycle that is a common factor of all of the clocks. However, these techniques are still synchronous in nature, and can mask design defects that may become apparent only when the hardware is manufactured.
More advanced techniques have been developed that allow a simulator or emulator to process events in parallel in a way that more closely approximates asynchronous behavior. These techniques essentially allow execution of events in different clock domains in parallel. In order to benefit from these techniques, it is necessary to partition a circuit design into different clock domains. The known methods for partitioning a circuit design into different clock domains require substantial effort by highly skilled circuit designers to manually partition the circuit into groups of components that correspond to different clock domains. For a complex integrated circuit, this effort is substantial and very time-consuming. Without a method for more efficiently partitioning a circuit into different clock domains, the electronics industry will continue to suffer from inefficient methods of partitioning netlists for circuits and systems that have multiple clock domains.
In accordance with the present invention, a method partitions a netlist into multiple clock domains. The number of clock domains is the number of primary input clocks plus one freerun domain. First, each functional block in the netlist is colored with a number of colors corresponding to the number of primary input clocks. Buckets are then created, with one bucket corresponding to a particular clock domain. Each functional block in the netlist is then placed in one of the buckets according to one or more partition criterion, which takes into account the color of logic that feeds a functional block and the color of logic that the functional block feeds. The result is that the original netlist is partitioned into multiple netlists, each of which corresponds to a single clock domain. These multiple netlists may be executed in parallel to emulate the function of the circuit represented in the netlist.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.